®
Intel IQ31244 Customer
Reference Board
User’s Manual
April 2004
Order Number: 252933-001
Contents
Contents
1.0 Introduction ...............................................................................................................................7
Features................................................................................................................................9
Electrical Specifications ......................................................................................................10
1.2.1 SATA Drive Enclosures .........................................................................................10
Environmental Specifications..............................................................................................10
Physical Characteristics......................................................................................................11
2.0 PCI-X Interface........................................................................................................................14
2.1 PAL Arbitration Circuit ........................................................................................................15
3.0 Intel 80321 I/O Processor.................................................................................................16
®
Interrupts.............................................................................................................................18
General-Purpose I/O Unit ...................................................................................................19
I C Bus Units ......................................................................................................................19
SDRAM EEPROM ..............................................................................................................20
Temperature Sensors.........................................................................................................20
Reset Supervisor ................................................................................................................20
3.7.1 Upgrading SDRAM ................................................................................................21
3.7.2 Installation and Removal of Memory Modules.......................................................21
2
4.0 Gigabit Ethernet Interface..................................................................................................22
®
Intel 82546EB Dual-Port Gigabit Ethernet Controller .......................................................22
5.0 SATA Interface........................................................................................................................23
Intel 31244 PCI-X to Serial ATA Controller.......................................................................24
Activity LEDs.......................................................................................................................25
®
6.0 Peripheral Bus Interface Unit ...........................................................................................26
Flash ROM..........................................................................................................................26
CompactFlash* ...................................................................................................................26
Console Serial Port.............................................................................................................27
JTAG Emulator Support......................................................................................................28
Hex Display.........................................................................................................................28
LEDs...................................................................................................................................28
7.0 ATX Power Connector.........................................................................................................29
8.0 Jumpers.....................................................................................................................................30
User’s Manual
3
Contents
Figures
®
Intel IQ31244 Customer Reference Board Block Diagram......................................................... 8
Component Layout Diagram (not to scale).................................................................................12
®
Intel 80321 I/O Processor Block Diagram ................................................................................17
®
Intel 80321 I/O Processor Interrupt Connections .....................................................................18
Peripheral Bus Interface Unit......................................................................................................26
Tables
Intel IQ31244 Customer Reference Board Power Requirements.............................................10
®
Environmental Specifications .....................................................................................................10
Physical Characteristics .............................................................................................................11
Documents and Manufacturers ..................................................................................................13
Primary PCI Bus.........................................................................................................................14
Rotation Scheme of the PAL Arbitration Circuit..........................................................................15
®
Intel 31154 133 MHz PCI Bridge GPIO Pin Assignments ........................................................18
GPIO Signal Definitions..............................................................................................................19
2
10 I C Device Addresses ................................................................................................................19
11 Supported SDRAM Configurations.............................................................................................21
12 Gigabit Ethernet Port Assignment ..............................................................................................22
13 SATA Port Assignment...............................................................................................................23
14 SATA Port Pin Assignment.........................................................................................................23
15 SATA JTAG Emulator Pin Assignment.......................................................................................24
16 SATA Port Pin Assignment.........................................................................................................24
17 SATA LED Header .....................................................................................................................25
18 Console Serial Port Connector ...................................................................................................27
19 Read-Only Rotary Switch ...........................................................................................................27
20 JTAG Emulator Pin Assignment.................................................................................................28
21 ATX Power Connector (J1).........................................................................................................29
22 Jumper Options ..........................................................................................................................30
4
User’s Manual
Contents
Revision History
Date
Revision
Description
April 2004
001
Initial release
User’s Manual
5
Contents
THIS PAGE INTENTIONALLY LEFT BLANK
6
User’s Manual
®
Intel IQ31244 Customer Reference Board
1.0
Introduction
®
The Intel IQ31244 Customer Reference Board (hereafter called “IQ31244”) is a FlexATX
®
®
motherboard based on the Intel 80321 I/O Processor. The Intel third-party part number for this
motherboard is MB-701.
This platform is capable of operating at a maximum of 100 MHz PCI-X on both the secondary and
®
®
Controllers on the secondary side of an Intel 31154 133 MHz PCI Bridge. The IQ31244 also
®
includes an Intel 82546 Dual-Port Gigabit Ethernet Controller, a 64-bit PCI-X expansion slot, and
®
various features on the 80321 peripheral bus interface (PBI). The Intel 31154 133 MHz PCI
Bridge provides a PCI-X bridge, which allows direct peer-to-peer communication between the
processor and the four 31244 PCI-X to Serial ATA Controllers on the secondary PCI-X 64-bit bus
with frequency of 100 MHz. The IQ31244 provides sixteen Serial ATA connectors, since each
®
Serial ATA has four SATA channels. The Intel 82546EB Dual-Port Gigabit Ethernet Controller
®
interface has two network ports. The Intel 80321 I/O Processor also provides the DDR SDRAM
memory controller. The IQ31244 processor peripheral bus interface operates at a frequency of
33 MHz frequency with flash ROM, CompactFlash*, UART, Hex Display LEDs, and rotary
switch.
User’s Manual
7
®
Intel IQ31244 Customer Reference Board
1.1
Features
Table 1.
Features and Descriptions
Feature
Description
Processor
•
Intel® 80321 I/O Processor
Options for the clock on 64-bit bus:
•
•
•
100 MHz PCI-X
Primary PCI
66 MHz PCI-X
66 MHz conventional PCI
•
•
Two RJ45 shielded magnetic LED gigabit connectors
Gigabit Ethernet debugging/download ports (using Intel® 82546EB
Ethernet Ports
Dual-Port Gigabit Ethernet Controller)
PCI Slot
•
•
64-bit PCI-X expansion connector
Intel® 31154 133 MHz PCI Bridge
PCI-X Bridge
•
•
64-bit 100 MHz PCI-X bus
Four Intel® 31244 PCI-X to Serial ATA Controllers
Secondary PCI
Serial ATA
•
•
Sixteen SATA connectors
Four Intel® 31244 PCI-X to Serial ATA Controllers
Flash ROM
•
•
•
•
•
•
•
8 MB Flash ROM 3.3 V—16-bit Flash
16-bit CompactFlash* PC Card Memory Mode
FlexATX form factor in ATX chassis with 300 W power supply
Eight GPIO pins
CompactFlash*
Form Factor
General-Purpose I/O
Hex Display
Two 7-segment Hex LED displays
Rotary Switch
Rotary/hex switch
RTC and NVRAM Supervisor
Microprocessor power-on reset with watchdog timer and real-time clock
•
•
85 dB
Buzzer
Frequency 2300 Hz
JTAG Port
Memory
•
ARM*-compliant JTAG 20-pin header
•
•
PC 1600 Double Data Rate (DDR) SDRAM (100 MHz clock rate)
256 MB 64-bit (expandable)
•
•
Board sources +3.3 V, +5 V, +12 V, and -12 V from ATX power supply.
Cores require +1.3 V, +1.5 V, and +2.5 V.
Onboard Power
Power LED
SATA LEDs
Temperature Sensor
Serial Port
•
•
•
•
•
“Power On” (green) LED indicator
2-pin header for each SATA channel
2-wire serial temperature sensor
One serial console port (16C550-compatible)
ATX desktop enclosure with 300 W power supply
Chassis
User’s Manual
9
®
Intel IQ31244 Customer Reference Board
1.2
Electrical Specifications
®
Table 2.
Intel IQ31244 Customer Reference Board Power Requirements
Current
(Typical)
Current
(Maximum)
Voltage
+3.3 V
+5 V
3.19 Amps
1.6 mAmps
0.0 Amps
0.0 Amps
4.56 Amps
2.28 mAmps
0.0 Amps
+12 V
-12 V
0.0 Amps
Most ATX power-supply units (PSUs) regulate off the 5 V signal. When no devices are drawing
from the 5 V supply, the ATX PSU does not supply 3.3 V correctly to the motherboard. To
compensate for this, it is recommended that a load (for example, an SATA hard drive) be added on
the 5 V rail from the PSU.
Note: The included 300 W power supply is sufficient to power up to four drives at one time. An
additional power supply is required to provide power for more than four drives. To estimate the
required power supply, estimate that each SATA drive draws approximately 2.8 A on the 12 V
supply.
1.2.1
SATA Drive Enclosures
It is highly recommended that the SATA drives are housed in an enclosure to reduce the
environmental noise that can affect performance. An example of a SATA four-drive enclosure is
the DE400 model from Storcase*:
1.3
Environmental Specifications
Table 3.
Environmental Specifications
Characteristic
Range
Operating temperatures
0–55 °C
0–95%
Relative humidity (non-condensing)
Storage temperatures
-55–125 °C
Note: A small amount of airflow is required to prevent the IQ31244 operating temperature from
exceeding 55 °C. When the ATX chassis cover is removed, an external fan is required to provide
adequate air flow within the chassis.
10
User’s Manual
®
Intel IQ31244 Customer Reference Board
1.4
Physical Characteristics
Table 4.
Physical Characteristics
Characteristic
Description
9.0" × 7.5" (228.6 mm × 190.5 mm)
Dimensions (width × height)
Form factor
FlexATX
PCI expansion slot
Expansion card slot
NOTE: Use only PCI-X expansion cards.
Power supply connector
ATX (Molex* 39-29-9202 or equivalent)
User’s Manual
11
®
Intel IQ31244 Customer Reference Board
1.5
Physical Configuration
Figure 2 (not to scale) shows the location of jumpers, connectors, and ICs on the IQ31244
motherboard. Refer to this figure when component locations are referenced later in the manual.
Figure 2.
Component Layout Diagram (not to scale)
J1
SERIAL PORT
ENGINEERING SAMPLE
VTT
CYCLONE MICROSYSTEMS INC.
IQ31244
J3
J2
U1
MB-701 REV E
GE PORT 0
GE PORT 1
LABEL
C3
C2
270-0701-05
C1
COPYRIGHT 2003
2.5V-A
TP1
R208
T1P.33V
R51
R1
J5
R2
R3
R4
R5
R6
R8
J4
EMULATOR
Q2
L1
C471
U8
1
TP4
U2
C8
C16
C4
R10
R14
R11
C6
C465
U6
C466
U42
C42
C88
R20
R15
+
+
J9
C9
TP20
C13
TP36
Y1
J7
R18
R22
R23
R19
R24
R25
C99
R30
C21
C94
Q1
Q9
R28
U5
Q 1 0
C473
L3
C17
R7
82546
L2
U4
R31
R32
R33
GIGABIT
R257
C123
R35
R37
R41
R42
C121
C124
U7
C464
C19
C20
R34
R36
R39
R40
ETHERNET
L23
C93
J6
U44
TP37 C129
C22
Q4
R46
R47
+
U10
TP2
R49
R50
R54
R55
TP5
R48
R56
GPIO-B
TP6
C18
R52
R53
R281
GND
Z14
U12
R499
1.5V
R 2 7 4
U11
BUZZER
GPIO-A
U9
+
R61
+
R57
R59
R62
R65
R66
R70
R58
R479
R490
R60
C23
R29
+
R478
R63
R498
R489
R69
R569
R477
R538
R476
R573
R567
R566
R67
C24
C25
U13
ARBITER PAL
R68
TP2266
TP2287
29
TP9
R497
R475
R488
U14
U18
R72
R474
R496
R487
R71
U17
R473
R542
R75
R76
R79
C200
R86
R73
R515
R535
R516
R527
TP8
30
R183
R74
U16
R77
R614
R78
R82
R88
R93
R615
R89
80321 I/O PROCESSOR
R80
R613
U15
R517
Q5
R81
R91
CR3
R87
CR4
R616
R617
R83
R548
R84
U19
31154 PCI-X BRIDG
R85
R90
R96
C27
R546
R95
TP44
TP43
C479
E
TP40
TP39
U21
C26
R94
R609
R472
R565
R179
R537
R471
R486
R494
R100
R101
R104
+
R495
R92
Z3
R106
U23
R98
R97
R38
R102
R103
R105
R109
R112
R113
R116
R119
R470
R469
TP42
TP45
R544
TP46
R325
R108
R110
R111
R115
R117
R118
R107
R180
Z4
R177
R485
R468
U20
U22
R114
R121
R178
R122
R552
S1
R493
R311
R467
R484
U40
R120
R124
R127
R130
Z5
Z6
Z7
R123
R126
R128
R466
R465
R526
R131
R492
R483
R547
R607
R125
R132
C463
R133
C486
R135
R608
R136 R137R138 R139
C487
R134
R129
R140
R141
R142
U24
U25
R621
J15
U3
U45
R145
R143
R144
R147
1
R146
R540
R543
C505
C502
R539
J10
R541
R534
R513
R525
R533
R150
R151
R149
R156
R157
COMPACT FLASH
R154
R148
R152
R153
R160
C512
+
R158
R159
R161
U32
R524
R532
R523
C382
R624
J38
U27
R162
U28
SATA 1
U29
SATA 2
U30
SATA 3
R559
U31
R623
U34
R165
R164
R166
R508
R531
SATA 0
R167
R168
GND
R522
R530
U33
U35
C525
R163
R170
R521
R529
R504
R520
R528
R501
R519
R500
TP18
TP19
2.5V
TP17
L4
C527
TP38
R171
R172
3V
J8
SATA 0
J16
SATA 1
Q6
Q7
TP7
C531
C39
TP31
TP29
TP32
TP33
TP28
TP34
J17
R173
TP47
C44
LED0
LED3
R463
R491
U26
TP24
R363
R364
GND
J32
R464
SATA 2
J18
SATA 3
J21
J22
J24
J25
J23
J26
J27
J29
J30
J34
J36
J28
J31
J33
J35
J20
R461
C415
C416
C399
C431
C427
C423
C407
C408
C439
C403
C404
C451
C452
C447
C435
C436
C459
C460
C411
C412
C455
C443
RESET
SW
Z1
Z2
R186
C432
C448
C400
C456
C428
C424
C440
C444
R462
C419
PWR
SW
C420
C421
C422
R185
J37
J19
Z12
SATA[3:0]
CR5
C453
C454
C433
C434
1
1
C461
C462
C417
C418
C457
C458
C413
C414
C445
C446
C409
C410
C441
C442
C437
C438
C401
C402
C429
C430
C449
C450
C425
C426
C405
C406
1
PWR ON
LED
R378
R377
B3214-01
12
User’s Manual
®
Intel IQ31244 Customer Reference Board
1.6
Reference Information
Table 5.
Documents and Manufacturers
Document
Manufacturer
•
Intel® IQ31244 PCI-X Motherboard with Serial ATA
Controllers and Ethernet Controller User’s Manual (252933)
•
•
•
•
•
Intel® 80321 I/O Processor Developer’s Manual (273517)
Intel® 80321 I/O Processor Datasheet (273518)
Intel® 80321 I/O Processor Design Guide (273520)
Intel® 31154 133 MHz PCI Bridge Datasheet (278821)
Intel® 31154 133 MHz PCI Bridge Developer’s Manual
(278848)
Intel® 31154 133 MHz PCI Bridge Specification Update
Intel Corporation Literature Sales
PO Box 5937, Denver, CO 80217-9808
(800) 548-4725
•
•
(300826)
Intel® 31244 PCI-X to Serial ATA Controller Datasheet
(273595)
•
•
•
•
Intel® 31244 PCI-X to Serial ATA Controller Design Guide
(273651)
Intel® 31244 PCI-X to Serial ATA Controller Developer’s
Manual (273603)
Intel® 82546EB Dual-Port Gigabit Ethernet Controller
Specification Rev. 1.1 (document under disclosure)
Intel StrataFlash® 28F640J3A Flash ROM Datasheet
(290667)
Texas Instruments Literature Response Center
P.O. Box 809066, Dallas, TX 75380-9066
(800) 477-8924
•
•
Texas Instruments* TL16C550 UART
Texas Instruments* TL7702B
Serial ATA Working Group
Serial ATA Specification, Revision 1.0
Microchip Technology
Microchip Technology* Serial EEPROM-93LC46
STMicroelectronics* NVRAM Supervisor-M41ST85W
STMicroelectronics
National Semiconductor Corp.
1111 West Bardin Road, Arlington, TX 760017
(800) 272-9959
National Semiconductor* LM75 Digital Temperature Sensor
PCI Special Interest Group
5440 SW Westgage Dr. Suite #217, Portland, OR 97221
(800) 433-5177
(503) 222-6190 (fax)
•
•
PCI-X Addendum to the PCI Local Bus Specification,
Revision 1.0a
PCI Local Bus Specification, Revision 2.2
•
•
ATX Specification, version 2.1
FormFactors.org
FlexATX Addendum to microATX Specification, version 1.0
CompactFlash* Association
P.O. Box 51537, Palo Alto, CA 94303
(650) 843-1220
CF+ and CompactFlash* Specification, Revision 1.4
(650) 493-1871 (fax)
email: infoflash@compactflash.org
User’s Manual
13
®
Intel IQ31244 Customer Reference Board
2.0
PCI-X Interface
The IQ31244 contains two 64-bit PCI-X buses. The primary PCI bus, clocked at up to 100 MHz,
®
®
interfaces with the Intel 80321 I/O Processor, the Intel 82546 Dual-Port Gigabit Ethernet
®
Controller, the Intel 31154 133 MHz PCI Bridge, and the PCI-X expansion slot.
Note: The PCI-X expansion slot must be used for PCI-X cards only.
®
The secondary PCI bus, clocked at 100 MHz, provides the interface between the Intel 31154
®
133 MHz PCI Bridge and the four Intel 31244 PCI-X to Serial ATA Controllers.
In addition, the two buses can communicate with each other by means of the Intel® FW31154
133 MHz PCI-X Bridge. The primary bus and secondary bus can operate at different speeds and
modes independently of each other. Depending on the peripheral add-in card capability, the
primary bus can operate at either conventional PCI, PCI-X 66 MHz, or PCI-X 100 MHz. The mode
Table 6.
Primary PCI Bus
Type of PCI
Speed
Z4
Z3
PCI-X 100
PCI-X 66
100 MHz
66 MHz
66 MHz
Open
Open
Open
Closed
Open
Conventional PCI
Closed
14
User’s Manual
®
Intel IQ31244 Customer Reference Board
2.1
PAL Arbitration Circuit
The IQ31244 provides a Programmable Analog Logic (PAL) arbitration circuit on the primary
PCI-X bus. A rotating priority arbitration scheme with a host and three agents is used. The priority
priority requesting device. On reset, the host is granted the bus, and agent 0 (PCI-X bridge) has the
next-highest priority.
Table 7.
Rotation Scheme of the PAL Arbitration Circuit
Priority
Description
Intel® 80321 I/O Processor
Host
0
1
2
Intel® 31154 133 MHz PCI Bridge
Expansion slot
Intel® 82546 Dual-Port Gigabit Ethernet Controller
When an agent is “skipped”, priority is not returned to that agent until the next passing cycle. This
means that the agent is dropped from the highest priority to the lowest priority.
The arbiter has a time-out feature that functions as follows. Any PCI master which has requested
the bus, but has not started an access within 16 clocks of receiving a grant, is assumed to be broken
and the grant is rescinded.
When the PCI bus arbiter receives a request for the bus and there are currently no active
transactions on the bus, the arbiter immediately grants ownership to the requester.
When two or more requests are active, the bus is granted to the requester with the higher priority.
This approach ensures that all requesters are able to gain access to the bus in a reasonable time and
that a high-bandwidth PCI adapter cannot starve all other requesters off the bus. This arbitration
scheme conforms to the fairness doctrine described in the PCI Bus Specification, Revision 2.2.
The arbiter also implements bus parking. After a transaction is complete, if there are no requests
for the bus, the arbiter parks the bus at the last owner. When that device wishes to begin another
PCI transaction, it may do so without first requesting the bus. When another device requests the
bus, the arbiter can immediately remove bus ownership from the idle device where it is parked.
After reset or power-up the PCI bus is parked at the host.
Highest arbitration priority is given to the host immediately succeeding the bus owner, active or
parked. Bus ownership is passed to the host with the next-highest priority and with an active bus
request.
User’s Manual
15
®
Intel IQ31244 Customer Reference Board
®
3.0
Intel 80321 I/O Processor
®
®
The Intel 80321 I/O Processor is based on the Intel XScale micro-architecture core (compliant
with ARM* architecture). The on-board 80321 processor supports 64-bit applications with
operating frequency of up to 100 MHz. The processor operates in conventional PCI mode or in
PCI-X mode as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
The processor has the following features:
®
• Intel XScale core
• PCI Local Memory Bus Address Translation Unit (ATU)
• Memory controller unit
• Peripheral Bus Interface (PBI)
• Application accelerator unit
2
• Two I C bus interface units
• Two DMA channels
• Performance monitoring unit
• Synchronous serial port unit
• Messaging unit
• Eight general-purpose I/O ports
16
User’s Manual
®
Intel IQ31244 Customer Reference Board
3.1
Interrupts
®
®
The Intel 80321 I/O Processor is built around an Intel XScale core, which has four external
interrupt lines designated XINT0# through XINT3#. In the 80321 processor, these interrupt lines
are not directly connected to external interrupts, but pass through a layer of external interrupt
®
Figure 4.
Intel 80321 I/O Processor Interrupt Connections
The external devices are AND-gated into designated interrupt signals. Therefore, the specific
®
device that generates the interrupt cannot be detected. However, the eight GPIO pins of the Intel
31154 133 MHz PCI Bridge are used to read interrupts from the specific device, as shown in
®
Table 8.
Intel 31154 133 MHz PCI Bridge GPIO Pin Assignments
GPIO
Signal
7
6
5
4
0
SATA 3 Interrupt
SATA 2 Interrupt
SATA 1Interrupt
SATA 0 Interrupt
Expansion Slot INTB#
18
User’s Manual
®
Intel IQ31244 Customer Reference Board
3.2
General-Purpose I/O Unit
®
The Intel 80321 I/O Processor has eight general-purpose I/O GPIO[7:0] pins to control or
monitor external devices in the I/O subsystem:
• The GPIO[0] and GPIO[1] signals are for CompactFlash* status.
• The GPIO[2] signal can be set to sound the buzzer. The buzzer can be disabled by adding a
jumper onto Z14.
• The Flash ROM signal VPEN is assigned to GPIO[4] to allow software connection for
code/data protection.
• The Flash ROM signal STS is assigned to GPIO[5] to allow interrupt input from the Flash
ROM.
2
• The GPIO[6] and GPIO[7] signals are for the I C bus.
Table 9.
GPIO Signal Definitions
GPIO
Signal
7
6
5
4
3
2
1
0
Port 0 SCL
Port 0 SDA
Port 1 SCL/Flash_VPEN
Port 1 SDA/Flash_STS
Watchdog Timer
Buzzer
Compact Flash Wait
Compact Flash Ready/Busy
3.3
I2C Bus Units
2
2
®
The IQ31244 has two Inter-Integrated Circuit (I C) bus units. The first I C bus interfaces the Intel
2
80321 I/O Processor with the other I C peripherals and microcontrollers for system management
functions. Both buses allow the processor to serve as a master and slave device residing on the I C
bus. The first I C has four components attached to the processor: the SDRAM EEPROM, the two
2
2
2
2
second I C bus interface is through J15, a 4-pin header with pin 1 as SDA and pin 2 as SCL.
2
Table 10.
I C Device Addresses
Designator
Device
Function
Address
DDR SDRAM
J8
Memory configuration
1010 0000
EEPROM DIMM
LM75
U35
U8
Temperature sensor
Temperature sensor
Reset supervisor
1001 000x
1001 001x
1101 000x
LM75
U7
ST-M41ST85W
User’s Manual
19
®
Intel IQ31244 Customer Reference Board
3.4
3.5
SDRAM EEPROM
The EEPROM located on the SDRAM module contains identification and configuration
information. Start-up code must read this information on power-up and must properly configure the
®
Intel XScale processor to the SDRAM type.
Temperature Sensors
The National Semiconductor* LM75 temperature sensors have over-temperature trip points that
trigger an interrupt when crossed. The sensors are placed on the board at U8 and U35. They share
an interrupt line to the processor. Polling the two devices is required to determine which device
triggered the interrupt. The sensors are placed in interrupt mode by the Breeze* initialization code
default over-temperature point is 80 °C. The sensors can be read for a temperature reading at any
time. Reading after an interrupt clears the interrupt. The sensor does not interrupt again until the
temperature drops below the hysteresis value (default is 75 °C) and rises again beyond the trip
point. Consult the LM75 datasheet for more details on programming the temperature sensors.
3.6
Reset Supervisor
®
The STMicroelectronics* M41ST85W supervisor chip is connected to the Intel 80321 I/O
2
Processor through its I C bus interface. The supervisor controller uses a 512-bit, static CMOS
SRAM organized as 64 words by 8 bits wide. This controller is driven by a 32.768 KHz clock. It
features the time-of-day clock/calendar function, status/control of alarm, watchdog timer, and
power-fail voltage monitoring (used by Ethernet LAN Power Good). The eight clock address
locations contain the century, year, month, date, day, hour, minute, second, and tenths/hundredths
of a second in 24-hour Binary Code Decimal (BCD) format. Corrections for 28-, 29- (leap year—
valid until year 2100), 30- and 31-day months are made automatically.
The supervisor chip is supplied with a SNAPHAT package, which has a crystal and a battery for
backup during power failures. The SNAPHAT comes in two battery sizes (48 or 120 mAh).
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®
Intel IQ31244 Customer Reference Board
3.7
DDR SDRAM
®
The Intel 80321 I/O Processor integrates a memory controller unit (MCU) to provide a direct
interface between the processor and its local memory subsystem.The IQ31244 board is equipped
with a 184-pin DIMM socket to accept a +2.5 V Double Data Rate (DDR) synchronous DRAM
module with or without error correction code (ECC). This DDR SDRAM interface provides a
direct connection to a reliable high-bandwidth memory subsystem. The socket accepts a 64- or
72-bit DDR SDRAM module with up to two 512 MByte banks for a maximum of 1 GByte. The
SDRAM is accessible by the processor and the PCI bus by means of address translation by the
memory management unit of the 80321.
3.7.1
Upgrading SDRAM
The IQ31244 board is equipped with unbuffered DDR SDRAM with ECC inserted in the 184-pin
DIMM socket. The memory can be expanded by inserting a maximum-sized memory module of
Table 11.
Supported SDRAM Configurations
Type
Size
Class
Total Memory Size
64 MBytes
CL2
8M × 64
8M × 72
CL2 ECC
CL2
64 MBytes
128 MBytes
128 MBytes
256 MBytes
256 MBytes
512 MBytes
512 MBytes
1 GByte
16M × 64
16M × 72
CL2 ECC
CL2
32M × 64
32M × 72
64M × 64
64M × 72
128M × 64
128M × 72
DDR 200
CL2 ECC
CL2
CL2 ECC
CL2
CL2 ECC
1 GByte
3.7.2
Installation and Removal of Memory Modules
Installation and removal of DIMMs on the IQ31244 are simple procedures and require no special
tools. Remove the adapter module from the motherboard before its memory configuration is
changed. Take care to avoid static discharge while contacting the module or the motherboard. Wear
a properly connected grounding strap while installing or removing memory modules on the
IQ31244.
Align the key cut-outs of the module to the key pins of the DIMM socket. The memory module
must be inserted vertically, and the latches on the socket must engage the mounting holes on the
DIMM module. Be sure that the latches on both sides of the module are properly engaged.
User’s Manual
21
®
Intel IQ31244 Customer Reference Board
4.0
Gigabit Ethernet Interface
®
The IQ31244 includes an Intel 82546EB Dual-Port Gigabit Ethernet Controller on the primary
PCI-X bus. Each port connector, J2 and J3, has a LINK indicator LED on the left side and a
ACTIVITY indicator LED on the right side.
Table 12.
Gigabit Ethernet Port Assignment
Pin
Symbol
1
2
T/R1ct
T/R1-
3
T/R1+
T/R2+
T/R2-
4
5
6
T/R2ct
T/R0ct
T/R0+
T/R0-
7
8
9
10
11
12
13
14
15
16
T/R3-
T/R3+
T/R3ct
LED1-
LED1+
LED2-
LED2+
4.1
Intel® 82546EB Dual-Port Gigabit Ethernet Controller
®
The Intel 82546EB Dual-Port Gigabit Ethernet Controller is a single PCI device with two full
Gigabit Ethernet MAC and PHY layer functions. It provides two standard IEEE 802.3 Ethernet
interfaces with 1000Base-T, 100Base-TX, and 10Base-T applications. The controller manages dual
MAC and PHY functions and directly interfaces with the PCI-X primary bus.
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User’s Manual
®
Intel IQ31244 Customer Reference Board
5.0
SATA Interface
®
®
On the IQ31244, the Intel 31154 133 MHz PCI Bridge interfaces with four Intel 31244 PCI-X to
Serial ATA Controllers on the 64-bit data secondary PCI-X bus clocking at 100 MHz. The 31244
chip transmits and receives commands to one of the four Serial ATA channel with speeds of
1.5 Gb/s and 8b/10b encoded data. Each 31244 controller (U27–U30) has four channels. There is a
total of sixteen SATA signal connectors (J21–J36) on the IQ31244 board. The IQ31244 is
configured for Direct Port Access (DPA) mode to allow independent control of the SATA devices.
Table 13.
SATA Port Assignment
SATA
Controller
Port 0
Port 1
Port 2
Port 3
LED
U27
U28
U29
U30
J24
J28
J32
J36
J23
J27
J31
J35
J22
J26
J30
J34
J21
J25
J29
J33
J16
J17
J18
J20
Table 14.
SATA Port Pin Assignment
Pin
Symbol
1
2
3
4
5
6
7
Ground
A+
A-
Ground
B-
B+
Ground
User’s Manual
23
®
Intel IQ31244 Customer Reference Board
5.1
SATA JTAG Interface
®
The Intel 31244 PCI-X to Serial ATA Controller JTAG interface is provided to assist on-board
for the JTAG (J38) on PCI-X to Serial ATA controller (U30).
Table 15.
SATA JTAG Emulator Pin Assignment
Pin
Signal
1
2
TRST#
GND
TCK
3
4
GND
TMS
GND
TDI
5
6
7
8
GND
TDO
GND
9
10
5.2
Intel® 31244 PCI-X to Serial ATA Controller
Each of the 31244 chips transmits and receives commands to one of the four Serial ATA channels.
Direct Port Access or DPA mode is hard-wired on each of the SATA controllers. DPA mode allows
independent control of the SATA devices, allowing multiple disks to be accessed at the same time.
®
Refer to the Intel 31244 PCI-X to Serial ATA Controller Developer’s Manual (273603) for more
information.
Table 16.
SATA Port Pin Assignment
Pin
Signal
1
2
3
4
5
6
7
Ground
A+
A–
Ground
B–
B+
Ground
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Intel IQ31244 Customer Reference Board
5.3
Activity LEDs
The IQ31244 provides a group of four sets of headers for each SATA controller located on the
bottom-left corner of the board. Each set of headers represents a cathode and anode of an LED for
each port of the SATA controller. The SATA activity can be shown through a LED when it is
connected to the headers. The activity of the SATA controller can displayed in two modes. In DPA
mode, each port has its own LED signal. The group of headers (J16, J17, J18, and J20) are assigned
to each SATA controller (U27, U28, U29, and U30). Z12 is the header for congregated SATA LED
signals. Pin 1 is the cathode and pin 2 is the anode of the LED. The LED symbol is shown on the
board.
Table 17.
SATA LED Header
Pin
Cathode
Pin Anode
LED
Port
1
2
3
4
5
6
7
8
LED0
LED1
LED2
LED3
0
1
2
3
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25
®
Intel IQ31244 Customer Reference Board
6.0
Peripheral Bus Interface Unit
The Peripheral Bus Interface (PBI) unit is a data-communication path to various components of the
®
Intel I/O processor hardware system that do not have PCI bus interfaces and do not optimally
reside on the PCI bus. Since the peripheral bus has low bandwidth, the PBI incorporates a 1 KByte
®
data queue to satisfy the 128 byte ADB requirement of the Intel bus. The bus is selected to
operate at 33 MHz. The PBI bus includes six chip enables. The PBI chip enables activate the
appropriate peripheral device when the address falls within one of the six programmable address
ranges. All six address ranges incorporate functionality that optimizes an interface for Flash
Memory devices.
Figure 5.
Peripheral Bus Interface Unit
6.1
6.2
Flash ROM
The IQ31244 provides 8 MBytes of sector-programmable Flash ROM for non-volatile code
storage on the peripheral bus. The Flash ROM (designator U22) is an Intel 28F640J3 type (or
equivalent). On the IQ31244, the Flash ROM uses a 16-bit interface. The IQ31244 can be
programmed using the JTAG emulator (J5).
®
CompactFlash*
The IQ31244 provides a vertical socket (J10) for a CompactFlash* Storage Card as additional flash
memory storage. It is accessible by means of the 16-bit Peripheral Bus Interface (PBI). The
CompactFlash Storage Card functions in PC Card ATA memory mode. For more details on the
CompactFlash* functionality, refer to the CF+ section in the CompactFlash* specification,
revision 1.4.
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Intel IQ31244 Customer Reference Board
6.3
Console Serial Port
A single console serial port with a DB-9 line interface is included on the IQ31244. This port can be
connected to a host system through the DB-9 connector from the rear I/O.
Table 18.
Console Serial Port Connector
Pin
Signal
Description
Not used
1
2
3
4
5
6
7
8
9
N/C
RXD
TXD
N/C
Receive data
Transmit data
Not used
GND
N/C
Signal ground
Not used
RTS
CTS
N/C
Request to send
Clear to send
Not used
The serial port is based on a Texas Instruments* TL16C550 UART clocked at 1.843 Mhz. The
device can be programmed to use this clock with the internal baud rate counters. The serial port can
operate at speeds from 300 to 115,200 bps and can be operated in interrupt-driven or polled mode.
For a detailed description of the registers and device operation, refer to the TL16C550
6.4
Rotary Switch
Read-Only Rotary Switch
Table 19.
Bit
Signal
0
1
2
3
A
B
C
D
User’s Manual
27
®
Intel IQ31244 Customer Reference Board
6.5
JTAG Emulator Support
The IQ31244 provides a JTAG debugger interface at J5. This interface is compatible with the
Wind River* visionPROBE*. The JTAG emulator interface connects primarily through the JTAG
®
port of the Intel 80321 I/O Processor and can assert a reset to the 80321. The JTAG emulator
Table 20.
JTAG Emulator Pin Assignment
Signal
Pin
Pin
Signal
VTref
TRST#
TDI
1
3
2
4
Vsupply
GND
GND
GND
GND
GND
GND
GND
GND
GND
5
6
TMS
TCK
7
8
9
10
12
14
16
18
20
GND
TDO
SRST#
NC
11
13
15
17
19
NC
6.6
6.7
Hex Display
There are two seven-segment Hex LED displays (CR5). The two digits (MSB and LSB) utilize the
LEDs
The power-on LED can be plugged into J37 with pin 1 as the cathode and pin 3 as the anode.
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Intel IQ31244 Customer Reference Board
7.0
ATX Power Connector
implemented with a Molex* 39-29-9202 or equivalent. This power connector mates with a power
supply connector, Molex 39-01-2200 or equivalent.
Table 21.
ATX Power Connector (J1)
Pin
Signal
1
2
+3.3V
+3.3V
GND
+5V
3
4
5
GND
+5V
6
7
GND
PW-OK
5VSB
+12V
+3.3V
-12V
GND
PS-ON
GND
GND
GND
-5V
8
9
10
11
12
13
14
15
16
17
18
19
20
+5V
+5V
User’s Manual
29
®
Intel IQ31244 Customer Reference Board
8.0
Jumpers
Table 22.
Jumper Options
Designator
Type
Configure
Description
Enables spread-spectrum clocking
on the primary PCI clocks.
J4
2-pin post Add shunt to enable
Shunt on
J11, J12, J13, J14
3-pin post Pin 1 and pin 2 = DPA Mode
Pin 2 and pin 3 = Master/Slave
SATA mode selection
Shunt on
J19
J37
3-pin post Pin 1 and pin 2 = power by switch
Pin 2 and pin 3 = auto power-on
System power by switch
Power-on LED
Pin 1 = Cathode
3-pin post
Pin 3 = Anode
J38
Z1
10-pin post JTAG for U30 SATA controller
2-pin post Chassis “RESET SW” cable
2-pin post Chassis “PWR SW” cable
SATA controller JTAG
Power reset switch
Power switch
Z2
Open = 100 MHz
2-pin post
Z3
Z4
Primary clock
PCI-X mode
Closed = 66 MHz
Open = PCI-X mode
2-pin post
Closed = PCI mode
Z5
Z6
2-pin post Add a shunt to the post
2-pin post Add shunt to enable
2-pin post Add shunt to enable
2-pin post Add shunt to enable
2-pin post Add shunt to enable
CompactFlash* to interrupt XINT1#
PBI reset mode
Z7
PBI retry mode
Z12
Z14
Congregated LEDs
Buzzer
§ §
30
User’s Manual
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